An essential part of the fabrication of semiconductor chips, in particular memory chips, is testing the quality of the fabricated chip. In the context of quality assurance, tests are often carried out simultaneously on a multiplicity of chips as early as at the wafer level, in order to segregate defective chips or to be able to initiate corresponding repair measures as early as possible.
In modern chipmaking, in customary test methods by means of a tester a multiplicity of test modes are set (loaded) into the chip(s) to be tested and are executed and the test results are output to the tester. In this case, the test modes may be stored in the respective tester; chips are often also equipped with a corresponding test logic in which, inter alia, various test modes may also be stored.
Nowadays test modes are usually set in the chip to be tested via a serial interface with the aid of a bit string in which respective bit sequences are in each case allocated to a specific test mode. By means of the bit string, the test modes are activated/deactivated, for example, or specific parameters are set in a respective test mode, whereby a test mode can be altered or, by way of example, specific subfunctions of a test mode can be activated/deactivated. In this case, a complete bit string is always transmitted serially, the bit string including the bit sequences of all the test modes even if only a specific test mode is to be executed or changed.
On account of the ever more complex structure of the chips which accompanies advancing miniaturization, ever more extensive tests have to be performed with regard to the required quality assurance. However, this has the effect that the serially supplied bit strings generally become very long and the setting or changing of individual or a plurality of test modes accordingly takes up very much time and, under certain circumstances, may even become time-critical. This problem occurs primarily when one or more test modes are changed over multiply during a test, which in practice may indeed be the case several thousand times per test. This means in practice that owing to time problems tests can often only be carried out inadequately or not at all, with the result that it is necessary to reckon with an increased rate of deficient chips that have reached the market. Furthermore, the very long bit strings required for complex chip structures cannot be handled by all test systems, since the bit width of all the registers in a test system is limited with regard to hardware. This can lead to significant overhead times in production.